1. Field of the Invention
This invention relates in general to a method for forming dual damascene, and more specifically relates to a method for forming dual damascene by means of shallow dummy metal-line pattern.
2. Description of Related Art
In many high-integration semiconductor devices, there are more than two layers of interconnect metal layer, which are called multilevel interconnects for the purposes of forming wiring line structures. The process of multilevel interconnects usually provides a first or a lower layer structure of metal wiring and interconnect, then forms a second layer of metal wiring for connecting the first layer of metal wiring and interconnect. The first layer of metal wiring is polysilicon or metal layer and electrically connects to the drain/source of the device within the substrate.
As the sizes of the devices become smaller and smaller, the numbers of devices per unit area increase. As a result, the manufacture of low resist and high reliable interconnects to connect the devices is a significant problem for developing high quality integrated circuits in modern era.
At present, a method for forming metal interconnects, named dual damascene, provides a more stable and more progressive process to manufacture integrated circuits. Therefore, the dual damascene method has been widely applied to the VLSI process under 0.25 .mu.m, which can form high efficient and high stable structure of metal interconnects.
Referring to FIGS. 1A through 1E, they show a conventional process for forming dual damascene. First, as shown in FIG. 1A, a first inter-metal dielectrics 104 is formed on a semiconductor substrate 100 containing a first metal line 102, and the material of the first inter-metal dielectric layer 104 is silicon oxide (SiO.sub.2). Next, a stop layer 106, which is used to be an etch stop layer of a metal trench while etching the first inter-metal dielectric layer 104 thereafter, is formed on the first inter-metal dielectric layer 104 by means of chemical vapor deposition (CVD), and the material of the stop layer 106 is silicon nitride (SiNx) or similar matter. Next, a first photoresist pattern 108 of via hole is patterned on the stop layer 106, and then the stop layer 106 that is not protected by the first photoresist pattern 108 and the first inter-metal dielectric layer 104 are etched by anisotropic etching until a first opening 110 which is above the corresponding first metal line 102 is formed and the depth of the first opening is shallow.
Referring to FIG. 1B, after removing the first photoresist pattern 108, a second inter-metal dielectric layer 112 is formed on the whole stop layer 106 and filled inside the first opening 110. The material of the second inter-metal dielectric layer is the same as the first inter-metal dielectric layer 104, such as silicon oxide. Referring to FIG. 1C, a second photoresist pattern 114 is patterned on the second inter-metal dielectric layer 112, then the second inter-metal dielectric layer 112 that is not protected by the second photoresist pattern 114, the stop layer 106, and the first inter-metal dielectric layer 104 are etched by anisotropic etching. Therefore, a second metal-line trench 116 is formed through the first opening 110 so that the surface of the first metal-line 102 is exposed and a via hole 118 is formed. Besides, a number of third metal-line trench 120 are formed at one side of the second metal-line trench 116, and the area where these third metal-line trench 120 is so-called high integration region of metal-line trench 121. It should be noticed that the bottom of the second metal-line trench 116 and the top of the via hole 118 are communicated, and the stop layer 106 is exposed to the bottoms of the third metal-line trenches 120.
Referring to FIG. 1D, after removing the second photoresist pattern 114, a glue layer 122 is blanketed on the surface of the second inter-metal dielectric layer 112 and along the side walls and bottoms of the second metal-line trench 116, via hole 118 and the third metal-line trenches 120. The material of the glue layer 122 is titanium, titanium nitride, tantalum or tantalum nitride for providing a better glue ability between materials of adjacent layers, and also has the function of barrier to prevent spiking between the silicon surface of the semiconductor substrate 100 and conductor deposited thereafter. Next, a metal layer 124 is formed on the glue layer 122 and filled inside the second metal-line trench 116, the via hole 118 and the third metal-line trenches 120. With the help of chemical mechanical polishing (CMP), the surface of the metal layer 124 and the glue layer 122 where are higher than the second inter-metal dielectric layer 112 is plannarized as shown in FIG. 1E, and then the metal filled inside the second metal-line trench 116, the via hole 118, the third metal-line trench 120 forms the second metal line 116a, the via hole 118a for connecting the first metal line 102 and the second metal line 106a, and the third metal lines 120a.
After polishing the metal layer 124 higher than the second dielectric layer 112, the glue layer 122 is then polished. However, the material of glue layer 122 is different the metal layer 124 so that it is hard to remove. If the area of the glue layer exposed to be polished is large, it needs much time to remove the glue layer, which causes over polishing effect so that the erosion of the metal line or dielectric layer occurs, and therefore the thickness of the metal line is reduced. For a wider metal lines spacing, the erosion problem is not serious. When the line spacing become smaller, especially under 0.18 .mu.m of modem technology, the erosion of the metal line causing by the over polishing becomes more serious. In addition to the thickness of the metal line being reduced, it also increases the resistance of the metal line and reduces the conductivity of the metal line.
As the forgoing description, another conventional method that uses dummy metal-line pattern is provided to prevent reducing the thickness and increasing the resistance of the metal line due to over polishing. FIGS. 2A to 2E show cross-sectional views for forming dual damascene by means of dummy metal-line pattern. Referring to FIG. 2A, a first inter-metal dielectric layer 204 and a stop layer are formed on a semiconductor substrate 200 containing a first metal line 202, wherein the first inter-metal dielectric layer 204 whose material is silicon oxide is formed on the substrate 200, and the stop layer 206 whose material is silicon nitride is formed on the first inter-metal dielectric layer 204. Next, a first photoresist pattern 208 of via hole is patterned on the stop layer 206, and then portion of the stop layer 206 and the first inter-metal dielectric layer 204 that are not protected by the first photoresist pattern 208 are etched with anisotropic etching.
Subsequently, as shown in FIG. 2B, after removing the first photoresist pattern 208, a second inter-metal dielectric layer 212 whose material is the same as the dielectric layer 204 such as silicon oxide is formed on the stop layer 206 and is filled inside the first opening 210. Afterwards, as shown in FIG. 2C, a second photoresist pattern 214 which includes a intensive metal-line region 221 and a dummy metal-line region 223 is patterned on the second inter-metal dielectric layer 212. Then, the second inter-metal dielectric layer 212 and the stop layer 206 that are not protected by the photoresist pattern 214 are etched until the stop layer 206 is etched slightly whereby a second metal-line trench 216 and via hole opening 218 above the first metal line 202, a number of third metal-line trenches 220 defined by the intensive metal-line region 221, and dummy metal-line trench 226 defined by the dummy metal-line region 223 are formed. Therefore, the bottom of the second metal-line trench 216 and the top of the via hole opening 218 are communicated and the surface of the first metal-line 202 is exposed to the bottom of the via hole opening 218. Besides, the third metal-line trenches 220 whose bottom are slightly below the surface of the stop layer 206 are located at one side of the second metal-line trench 216, and the dummy metal-line trenches 226 whose bottom are also slightly below the surface of the stop layer 206 are located at the other side of the second metal-line trench 216.
Referring to FIG. 2D, after removing the second photoresist pattern 214, a glue layer 222 whose material is titanium, titanium nitride, tantalum, or tantalum nitride for increasing the glue ability between different layers is blanketed on the surface of the second inter-metal dielectric layer 212 and along side walls of the second metal-line trench 216 and along the side walls and bottoms of the via hole 218, the third metal-line trenches 220 and the dummy metal-line trenches 226. In addition, the glue layer 222 also has the function serving as a barrier that prevents the spiking between the silicon surface of the substrate 200 and conductor deposited thereafter. Afterwards, a metal layer 224 is blanketed on the glue layer 222 and is filled inside the second metal-line trench 216, the via hole 218, the third metal-line trenches 220 and dummy metal-line trenches 226. Finally, as shown in FIG. 2E, with the help of chemical mechanical polishing (CMP), a portion of the glue layer 222 and metal layer 224 higher than the second inter-metal dielectric layer 212 is polished, and then a second metal line 216a, a via hole 218a, and a number of third metal lines 220a and dummy metal lines 226a are formed.
According to the forgoing description, because the dummy metal-line region 223a composing of number of dummy metal lines 226a decreases the area of the glue layer which has to be removed, the polishing time can be reduced. Therefore, the thickness of the metal line does not have to be reduced which increases the resistance of the metal line as compared with conventional method. However, the dummy metal lines 226a cause parasitic capacitances between conducting lines and reduce the operation speed of devices when current flows through the devices.
Conclusively, there are number of disadvantages of the conventional methods, which are described as following:
(1) Without the help of the dummy metal-line pattern to form a structure of dual damascene, the over polishing for metal line due to CMP causes the erosion of the metal line. Especially, if the width between metal lines is too narrow, the thickness of metal lines PA1 (2) With the help of the dummy metal-line pattern to form a structure of dual damascene, the thickness of the metal lines. However, if the device turns on, it will increase the parasitic capacitor between conducting lines, which decreases the operation speed of the device.